Faculty: Computer facilities and computer science Chair: Applied mathematics and computer science Specialty: The software of computer-based systems Master's thesis theme: "Logical and parametric simulation of the MOS of the VLSI circuit" Teacher: Dr.Sci.Tech. Andrjuhin Alexander Ivanovich Absatract «Logical and parametric simulation of the MOS of the VLSI circuit»Subject of inquiry of the given operation is a consideration of main existing approaches and resources to simulation of faults of MOS, and also interactings of interconnections in the VLSI circuit. The purpose of operation - research of various paths of rise of adequacy of simulation of faults of the MOS of the VLSI circuit at a switching level, and also research of interacting of interconnections in the VLSI circuit. Possibility of parallel scalings for Boolean expressions allows to realize effectively algorithms for simulation of faults and pseudo-random generation of mustering tests. Logic simulationSimulation of behaviour of electronic digital devices now became an integral part of design automation and diagnosing of these arrangements. About the help of a logic simulation the following tasks are solved: Validation of logical operation DA,
Check of time responses of the digital device,
The analysis of a races of signals,
Construction of mustering tests,
Composition check of the mustering test concerning the defined class of faults,
Obtaining and shortening of the diagnostic information for retrieval of faults of the digital device.
Depending on the demands showed by practice, various methods of simulation DA and ways of their implementation are applied. Choice from assemblage of methods and algorithms of simulation is carried out by criteria, basic of which are: adequacy and high-speed performance. Adequacy is fathomed as a level of correspondence of results of simulation to real behaviour of the observed digital device. Simulation of the digital device can be divided into tasks of the statical and dynamic analysis. A basis of the statical analysis is synchronous simulation at which time delays of distribution безинерционных units are equal to clock tick of clocking of the arrangement. The clock tick is fathomed temporary as an interval on which state of external poles of the arrangement does not vary. Synchronous simulation allows to verify logic of operation of circuits. As simulation of faults of the arrangements manufactured on MOS is known, that, at usage of models of these arrangements, at a gate level has significant difficulties. Percent of real physical imperfection which are coated with these model faults, not less than 75 %. There are data, that the tests built for detection of constant faults, do not muster about 10-15 % of real defects MOS. Switching models are the most known way of the registration of features of MOS. They allow to inject a uniform way of simulation of main types of faults. Switching models present behaviour of the circuit, using thus such main electronic parts, as , the p-type, the load transistor, an explorer, the logical reactor or size. the n-typeParametric simulationFast growth of an operating frequency of digital systems, became a reason of that the main task of engineering and testing, began support of integrity of signals. Spurious capacitances and inductivity, and their effect on interconnections in the MOS of the VLSI circuit, now play a main role in correctness of operation and productivity of the large-scale integrated circuit. Under integrity of a signal, we shall fathom ability of a signal to oscillate right answers on the circuit. According to these remarks, the signal with good integrity has: - value of an electrical pressure in required boundaries; - fulfils all transitions for a required period. Main problems of integrity of signals are: - Weakening A signal, owing to an interaction term between signals; - extremely fast increment of an electrical pressure of a signal; - change of the voltage source; - break-down of a signal, owing to various time delays of reaching by a signal of various receivers. There are some directions of retrieval of solutions of these problems at engineering and manufacture, diagnosing of the VLSI circuit among which simulation of the VLSI circuit is selected exact enough for practice at representation by its distributed RLC-model. At writing this abstract, masters work is not completed yet. Final completion: January, 2007. The complete text of work and all substances on a theme can be obtained for the author or his head after the indicated date. |

Raspy-sany-e-zaochny-ky-vesna-2013-5k-mos-12z-Maj | 2012 International Conference on Future Optical Materials and Circuit Design | ||

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Abstract Y. V. Ladyzhensky, Y. V. Popoff. A program system for distributed event-driven logic simulation | Abstract Y. V. Ladyzhensky, Y. V. Popoff. A program system for distributed event-driven logic simulation | ||

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